1. Field of the Invention
Embodiments of the invention relate to electronic data transmission, and more particularly, in one or more embodiments, to multi-level signaling.
2. Description of the Related Art
In electronic data transmission, signals representing electronic data are transmitted from a transmitting component to a receiving component. The electronic data typically includes data symbols such as binary digits (which are often referred to as bits), i.e., 0's and 1's. In many applications, signals having two different voltage levels representing data symbols such as 0's and 1's have been widely used for such data transmission.
In certain applications, signals having more than two levels have been used to transmit electronic data. Such a signaling scheme is generally referred to as “multi-level signaling.” In a multi-level signaling scheme, the data rate can be increased without increasing the clock frequency or the number of channels. In such a scheme, transmitters generate multi-level signals, and receivers detect them, allowing multiple (k) bits to be transmitted or received as one of 2k possible voltages at each clock edge or at least once per clock cycle. A multi-level signaling scheme allows two or more bits of data to be simultaneously transmitted by multiple signal levels, thereby increasing the data throughput for a given operating frequency.
In certain instances, the term “multi-level signaling” is also referred to as multi-level pulse amplitude modulation or M-PAM signaling. In such a case, the number of signal levels is indicated by a number before the acronym “PAM.” For example, a PAM signaling scheme using four signal levels is represented by 4 PAM. Similarly, a PAM signaling scheme using eight signal levels is represented by 8 PAM.
FIG. 1 is a graph illustrating a conventional multi-level signaling scheme using four voltage levels, i.e., 4 PAM. The four signal levels represent two-bits b0 b1. The highest voltage level over a high reference voltage VREFH represents the bits “11.” The second highest voltage level between the high reference voltage VREFH and a middle reference voltage VREFM (which is lower than VREFH) represents the bits “10.” The third highest voltage level between the middle reference voltage and a low reference voltage VREFL (which is lower than VREFM) represents the bits “01.” The lowest voltage level lower than VREFL represents the bits “00.” The two bits are transmitted as a single multi-level symbol at every clock edge by transferring an appropriate one of the four voltage levels. Therefore, the data rate of the signaling scheme just described is twice that of a 2-PAM system.
Referring to FIG. 2, a conventional transmitter circuit 200 for generating voltage levels under a 4 PAM signaling scheme will now be described. To provide the voltage levels to transmit a 4-PAM symbol, the transmitter circuit 200 sinks a predetermined amount of current for that symbol. In particular, each symbol is associated with a distinct amount of current.
The transmitter circuit 200 includes a voltage source VDD, a resistor R, a first transistor TR1, a second transistor TR2, a first current source CS1, a second current source CS2, a first node N1, and a signal output VOUT. The resistor R is connected between the voltage source VDD and the first node N1. The first node N1 is electrically connected to the signal output VOUT. Each of the first and second transistors TR1, TR2 is connected to the first node N1 at its source/drain. The drain/source of the first transistor TR1 is connected to the first current source CR1 which provides a current of 2I. The drain/source of the second transistor TR2 is connected to the second current source CR2 which provides a current of I.
To transmit the bits “11,” the transmitter circuit 200 sinks no current by turning off both of the first and second transistors TR1, TR2, and the signal output VOUT is pulled up to VDD. To transmit the bits “10,” the transmitter circuit 200 sinks an amount of current I by turning on the second transistor TR2 only, thereby providing VDD−RI at the signal output VOUT. To transmit the bits “01,” the transmitter circuit 200 sinks an amount of current 2I by turning the first transistor TR1 only, thereby providing VDD 2RI at the signal output VOUT. To transmit the bits “00,” the transmitter circuit 200 sinks an amount of current 3I by turning on both of the first and second transistors TR1, TR2, thereby providing VDD−3RI at the signal output VOUT.
In the transmitter described above, when generating three out of the four signal levels (e.g., those representing “00”, “01”, and “10”), power is dissipated because there is a current flow through the resistor R in the circuit. In other words, three out of four signal levels consume static power. It should be understood that the translation of the two sequential binary bits into multiple voltage levels need not follow exactly as it has been described thus far. For example, the bits “00” could be encoded as the highest voltage level, rather than as the lowest level, as has thus far been illustrated. Other alternative exist as well, including the well known gray-coding which would order the levels as follows: “00”, “01”, “11”, and “10.”